1. Field of the Invention
The present invention relates to a display using a plasma display panel (hereinafter a PDP) in which charges remain according to a state attained when an operation is halted and the charges affect display, to a driving method for the display, to a wave generating circuit for storing data concerning a wave and its generation in a ROM, consecutively reading the stored data, and converting the data into a wave, and to a planar matrix type display including the wave generating circuit.
In recent years, earnest requests have been made for a smaller thickness, more diverse display information and conditions for installation, a larger screen, and higher definition in the field of displays. There is an increasing demand for a display meeting these requests. Thin displays fall into various types which are represented by an LCD, fluorescent character display tube, EL, PDP, and the like. Among these thin displays, a display using a PDP is, above all, drawing attention because of its superb characteristics such as no flicker, ease in making the screen thereof larger, high luminance, a long service life, and the like.
2. Description of the Related Art
In a triple-electrode surface-discharge PDP, after writing is performed so that discharge selectively occurs according to display data between address electrodes and a second electrode which constitute pixels, a common sustaining discharge signal is applied between a first electrode and the second electrode so that sustaining discharge is performed at the pixels that have been discharged during writing, and thus display is achieved. During sustaining discharge, a pulsating signal is applied to the first and second electrodes a plurality of times with the polarity thereof alternated at every application. Discharge is therefore performed for a number of pulses, whereby the brightness of display is defined. After sustaining discharge is completed, a reset is executed in order to bring all pixels to the same state. Thereafter, the above operation is repeated in order to achieve display. In this kind of PDP display, a microcomputer is generally used for the above control operation. When a power switch is turned on, the microcomputer executes initialization in the same manner as an ordinary one. First, self-erasure accompanied by application of a full-screen pulse and sustaining discharge are repeated for several cycles. Thereafter, repetition of a cycle of normal reset, addressing, and sustaining discharge is started.
For driving a PDP, a large power at a voltage that is higher than the voltage needed for a logic circuit including a microcomputer is necessary. A power supply for the PDP is therefore separate from a power supply for the logic circuit. A large-capacitance capacitor or the like that withstands a high voltage is used to stabilize the power supply for the PDP. Therefore, when a power switch is turned off, the voltage of the power supply for the PDP decreases more slowly than that of the power supply for the logic circuit. When the voltage of the logic circuit power supply reaches a level not permitting the logic circuit to operate, outputting control signals ceases. The PDP halts in an immediately preceding state. In other words, the state in which the PDP halts is determined according to the timing of stopping supply of power, but the halt state is not finalized. Since the halt of the PDP is not finalized, the states of cells in the PDP, or more particularly, the states of wall charges vary depending on whether a state immediately before the halt is a reset period, addressing period, or sustaining discharge period. Depending on the halt state, charges remain on the surface of a dielectric membrane. If the cells are left in this state for a prolonged period of time, the gas in the cells is re-bonded with wall charges and neutralized. However, negative and positive wall charges remain on X electrodes and Y electrodes respectively. When these kinds of residual charges exist, there arises a problem that a reset is not achieved normally and an erased state is not attained. When a state preceding a reset period is not erased, normal discharge is not achieved during a succeeding addressing period and sustaining discharge period. Previous display data is displayed until full-screen writing is executed again during a reset period succeeding the sustaining discharge period in order to achieve erasure. When the previous display data is displayed, a problem that an observer of the PDP is given a quite peculiar feeling occurs.
It is conceivable that even if charges remain at the time of a halt, discharge for full-screen erasure is executed reliably by raising the voltage of a full-screen writing pulse. For this purpose, the ability of a cell structure and drive circuit to withstand a high voltage must be improved. This poses a problem that the scale of circuitry increases.
In the aforesaid operations, a pulsating signal is applied between electrodes in order to trigger discharge. As a circuit for generating this kind of pulsating signal, a circuit that stores data representing a signal concerning a wave and its control in a ROM in units of a basic period of wave generation, reads the data consecutively from the ROM, and thus generates the wave is adopted widely. Single reading may not be able to provide a required quantity of data. In this case, data whose cycle is a basic period is split into a plurality of items and then stored. Reading is performed a plurality of times during each basic period so that a required quantity of data can be output.
The present applicant has disclosed, in Japanese Unexamined Patent Publication (Kokai) No. 4-284491, a driving wave generating circuit that is dedicated to a PDP display and that includes a ROM. As a driving method for achieving gray-scale display in a PDP display, a multiple addressing method is adopted generally. According to the multiple addressing method, one display frame is divided into a plurality of subframes; sustaining periods within the subframes, which determine an effective luminance, are set to have a given ratio; and gray-scale data is displayed during subframes, which are weighted differently according to gray-scale levels; thus gray-scale display is achieved. A driving wave and control signals to be applied during one subframe are stored in the ROM. The length of a sustaining period is defined by the repetition frequency of a repetitive component of the driving wave.
In the field of PDP displays, the necessity of controlling driving of a panel by drivers more precisely has been discussed in an effort to further improve display quality and upgrade durability. It is therefore required to produce a more precise driving wave that is supplied to each driver. However, for producing a driving wave more precisely, the storage capacity of a ROM must be expanded and a quantity of data to be read from the ROM during a basic period must be increased. This means that the speed of reading data from the ROM must be raised. However, when an effort is made to raise the speed of reading the ROM, it becomes necessary to use a high-speed ROM. This poses a problem that the cost of a ROM increases. As far as the PDP display is concerned, therefore, a method to produce precise driving waves readily has not been realized.
This situation is not limited to a wave generating circuit used for a PDP display. The same applies to a wave generating circuit used for any other purpose. The foregoing problems occur in common when an attempt is made to produce precise waves.